1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) integrated circuits. More particularly, the present invention relates to a method and apparatus for encrypting a data stream used to program an FPGA device.
2. Background of the Invention
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general purpose logic circuits, called cells or blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain sequential elements such as flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for manufacture.
FPGAs may typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as Oxide Nitrogen Oxide (ONO) antifuse, Metal- Metal (M-M) antifuse, Static Random Access Memory (SRAM) memory cell, Flash Erasable Programmable Read Only Memory (EPROM) memory cell, and electronically Erasable Progammable Read Only Memory (EEPROM) memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, a NMOS transistor may be used as the switch to either connect or leave unconnected two selected points (A,B) in the circuit. The source and drain nodes of the transistor may be connected to points A, B respectively, and its gate node may be directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical “1” or “0”, the switch can be turned on or off and thus point A and B are either connected or remain unconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs may store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory (CM) determines the cell's functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
Design software may be used to program the FPGA. The design software may compile a specific configuration of the programmable switches desired by the end-user, into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is fed into the FPGA and used to program the configuration memories for the programmable switches. The bitstream is the data-pattern to be loaded into the CM that determines whether each memory cell stores a “1” or “0”. The stored bit in each CM controls whether its associated transistor switch is turned on or off. End users typically use software to create the bitstream after they have simulated and, tested the design for the FPGA.
Referring to the flow chart of FIG. 1, a designer or end user programs an FPGA 100. The design software assembles the configuration data into a data stream 110. This act may also be performed by software personnel. The data stream may be stored on a source external to the FPGA 120. On start up, the external source sends the data stream to the FPGA 130. Once in the FPGA, the data stream configures the RAM or PROM within the FPGA.
In a FPGA that uses a data stream that is downloaded from an external source, a person may be able to intercept the data stream as it is being loaded onto the FPGA, between acts 120 and 130 of FIG. 1. This may allow such a person to reverse engineer the IC if he or she is able to read the data stream.